This invention relates to a semiconductor memory device, more specifically to the arrangement of its bit lines and their connections to the data bus.
A semiconductor memory device has a memory cell array from which bit lines carry data to sense amplifiers, which place amplified data on an internal data bus. The bit lines and data bus lines are actually complementary pairs of lines, one carrying the data value and the other the inverse of that value.
Modern semiconductor memory devices are frequently subdivided into two or more memory cell arrays, each with separate bit lines and sense amplifiers which may be shared by adjacent memory cell arrays, and have two or more pairs of data bus lines. Interconnections between the bit lines and data bus lines are controlled by switching elements, called transfer means, that operate in response to column signals. In a device with two pairs of data bus lines, for example, each column signal selects two pairs of bit lines, connecting one bit line pair to one data bus pair, and the other bit line pair to the other data bus pair.
In the prior art, the bit line pairs are laid out in an order that alternates between one data bus line and the other. This scheme permits the two bit line pairs selected by the same column signal to be disposed side by side, but has the disadvantage that each bit line must be connected to the data bus at a separate node. This imposes a limitation to the reduction in the bit line pitch, and hence to the increase in the degree of integration.